1. Field of the Invention
The present invention relates to a semiconductor device and method of fabricating the same and, more particularly, to a mask ROM cell and method of fabricating the same, which prevents short channel effect.
2. Discussion of Related Art
In general, a mask ROM is composed of combination of a depletion transistor and enhanced transistor. The depletion transistor has negative threshold voltage according to depletion ion implantation, and is turned on when 0V is applied to its gate electrode. The enhanced transistor is formed in a manner that count-doping is performed to the channel region of the depletion transistor through code ion implantation, to have approximately 0.7V of threshold voltage, serving as the OFF transistor of mask ROM.
A conventional mask ROM cell and method of fabricating the same are explained below with reference to the attached drawings. FIG. 1 is a perspective view of a conventional mask ROM. As shown in FIG. 1, a plurality of impurity diffusion regions 13 are formed in a P-type semiconductor substrate 11 in one direction, having a predetermined distance therebetween, and a gate insulating layer 14 is formed on semiconductor substrate 11. A plurality of gate lines 15a are formed on gate insulating layer 14 in a predetermined interval, being perpendicular to plurality of impurity diffusion regions 13. In the formation of the gate insulating layer, thermal oxide layer 14a formed on each impurity diffusion region 13, is thicker than portions of the gate insulating layer, placed on region except the impurity diffusion regions.
FIGS. 2A to 2D are cross-sectional views showing a method of fabricating the conventional mask ROM cell. Referring to FIG. 2A, B+ impurity ion is implanted into the overall surface of P-type semiconductor substrate 11 for controlling the threshold voltage. Referring to FIG. 2B, a photoresist 12 is coated on semiconductor substrate 11, and patterned through exposure and development. High-concentration N-type impurity ion implantation is carried out to the overall surface of semiconductor substrate 21 using the patterned photoresist 12, to form plurality of impurity diffusion regions 13 in semiconductor substrate 11 in one direction, having a specific distance therebetween.
Referring to FIG. 2C, photoresist 12 is removed, and thermal oxidation is performed to the surface of semiconductor substrate 11 in which plurality of impurity diffusion regions 13 are formed, forming gate insulating layer 14. Here, thermal oxide layer 14a formed on impurity diffusion regions 13 formed by the impurity implantation, is thicker than portions of gate insulating layer 14, placed on the region other except impurity diffusion regions. A polysilicon layer 15 is formed on the overall surface of semiconductor substrate 11 including gate insulating layer 14. Referring to FIG. 2D, a photoresist (not shown) is coated on polysilicon layer 15, and patterned through exposure and development. Polysilicon layer 15 is selectively removed using the patterned photoresist as a mask, to form plurality of gate lines 15a which are perpendicular to plurality of impurity diffusion regions 13.
In the aforementioned conventional mask ROM cell and method of fabricating the same, however, the impurities included in the impurity diffusion regions are diffused when the semiconductor substrate is thermally oxidized to form the gate insulating layer, so as to shorten the distance between the impurity diffusion regions. This brings about short channel effect which reduces the channel region. Thus, there is a limitation in decreasing the cell size.
Accordingly, the present invention is directed to a mask ROM cell and method of fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a mask ROM and method of fabricating the same, which prevents the short channel effect, to reduce the size of mask ROM cell.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the mask ROM cell includes: a semiconductor substrate of a first conductivity type; a plurality of impurity diffusion regions of a second conductivity type, formed in the semiconductor substrate in one direction, having a predetermined distance therebetween; an insulating layer formed on a portion of the semiconductor substrate, corresponding to each impurity diffusion region; a gate insulating layer formed on only a portion of the semiconductor substrate between the impurity diffusion regions; and a plurality of conductive lines formed on the gate insulating layer and insulating layer in a predetermined interval, being perpendicular to the impurity diffusion regions.
The method of fabricating the mask ROM cell includes the steps of: preparing a semiconductor substrate of a first conductivity type; forming a plurality of impurity diffusion regions of a second conductivity type in the semiconductor substrate in one direction, having a predetermined distance therebetween; forming an insulating layer only a portion of the semiconductor substrate, corresponding to each impurity diffusion region; forming a gate insulating layer on only a portion of the semiconductor substrate between the impurity diffusion regions and forming a plurality of conductive lines on the gate insulating layer and insulating layer in a predetermined interval, the gate lines being perpendicular to the impurity diffusion regions.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.